1. Field of the Invention
The present invention relates to normalization and denormalization of data. More specifically, the present invention relates to normalizing data for cryptography processing and denormalizing the processed output.
2. Description of the Prior Art
Various hardware implementations for cryptography processing typically use software configured external processors to both normalize and denormalize data associated with cryptographic processing. Many methods for performing cryptography processing are well known in the art and are discussed, for example, in Applied Cryptography, Bruce Schneier, John Wiley & Sons, Inc. (1996, 2nd Edition), incorporated by reference in its entirety for all purposes. In order to improve the speed of cryptography processing, specialized cryptography accelerators have been developed that typically out-perform similar software implementations. Examples of such cryptography accelerators include the Hi/fn™ 6500 and BCM™ 5805 manufactured by Broadcom, Inc. of San Jose, Calif.
Cryptography accelerators, such as the BCM™ 5805 and Hi/fn™ 6500 chips, typically use software configured external processors to provide normalized data or normalized numbers for cryptography processing. Generally, a floating point number having no leading zeros is referred to herein as a normalized number. For example, 1.0×10−9 is in normalized floating point notation while 0.1×10−8 is not. In binary notation, the binary number “10100010” is a normalized binary number while the binary number “01010001” is an unnormalized number. Typically, an unnormalized number is converted to a corresponding normalized number by, in the example of the binary numbers, performing a shift operation. Using the example from above, the unnormalized binary number “01010001” is shifted left by one bit to provide the normalized binary number “10100010” which is now in condition to undergo cryptography processing.
Generally, modifying the result of the cryptography processing by the previous shift amount provides a corresponding denormalized number. Again, using the examples from above, if the unnormalized binary number “01010001” is shifted left one bit to form the normalized binary number “10100010” and cryptography processing on the normalized binary number “10100010” yields a result dataword “11001100”, then normalizing the result dataword “11001100” using the normalizing shift amount results in a “denormalized” result data word “01100110”.
Unfortunately, however, conventional external processors (such as central processing units, or CPUs), are not optimized to handle the myriad of normalization and denormalization operations required for cryptography processing. For example, both the BCM 5805™ and Hi/fn™ 6500 are typically configured to process data blocks that are much larger than those data blocks that a central processing unit is optimized to handle.
Most encryption schemes (such as Diffie-Hellman, RSA, and DSA) commonly have data block sizes on the order of 512 to 1024 bits or sometimes larger. Typical central processing units, however, can only handle blocks of data of 32 or 64 bits at a time. As one skilled in the art would appreciate, in order to accommodate these large data blocks, the CPU consumes large amounts of valuable processing. Since software configuration requires copying large amounts of data to intermediate storage during normalization and denormalization, the 512 or 1024 bit data blocks would be read and copied 32 bits at a time to intermediate storage and subsequently reread and recopied onto an output.
The processing of data blocks of 512 or 1024 bit using software configured 32 bit or 64 bit architectures substantially reduces cryptography processing throughput and increases software complexity. Furthermore, software configurations are typically slow, cumbersome, and nontrivial.
It is therefore desirable to have a system, method, and apparatus that provides for efficient hardware normalization and denormalization suitable for high speed cryptography processing.